With the development of multi-core system-on-a-chip (SoC), more memories are integrated thereon for facilitating operations of each core. Thereby, memories will definitely occupy the greater part of the chip area in the future, and become a significant factor influencing the performance of the SoC as well as consuming a considerable quantity of power. Accordingly, how to reduce the area and power consumption of memories effectively has become an important subject.
FIG. 1 shows a circuit diagram of a memory cell according to prior art. As shown in the figure, the memory cell according to the prior art comprises a first inverter 10′, a second inverter 20′, and an access port 30′. The input of the first inverter 10′ is coupled to the output of the second inverter 20′; while the output of the first inverter 10′ is coupled to the input of the second inverter 20′. Besides, the access port 30′ is coupled to the second inverter 20′ and a bitline (BL), and is coupled to a wordline (WL) as well. The access port 30′ is an N-type metal-oxide-semiconductor field-effect transistor (NMOS). Thereby, when the bitline is high level, the access port 30′ is turned on, causing a threshold voltage across the access port 30′, and hence reducing the effective voltage applied to the memory cell by the bitline. Moreover, FIG. 2 shows a circuit diagram of another memory cell according to prior art. As shown in the figure, the access port 30′ is replaced by a P-type metal-oxide-semiconductor field-effect transistor (PMOS). Thereby, when the bitline is high level and hence turning on the access port 30′, the voltage of the bitline can be transferred to the storage device without loss.
Generally speaking, when a single-ended memory cell reads or writes a logic “1”, the bitline will be firstly be maintained at a high level and the wordline will be turned on. Thereby, the single-ended memory cell cannot know how the bitline and wordline act and whether a logic “1” is being read or written. Hence, a memory cell is designed for writing or reading data in accordance with various levels of the bitline. When the memory cell reads, the voltage level of the bitline has to be changed to a relatively lower voltage level, so that data stored in the first inverter 10′ and the second inverter 20′ can be read via the access port 30′. When the memory cell writes, the bitline has to be changed to a high voltage level, so that data can be written to the memory cell composed by the first inverter 10′ and the second inverter 20′.
FIG. 3 shows a circuit diagram of another memory cell according to prior art. As shown in the figure, the memory cell 40′ according to the prior art comprises a first transistor 42′, a third inverter 44′, a second transistor 46′, and a fourth inverter 48′. A terminal of the first transistor 42′ is coupled to a dataline D′ and controlled by a wordline W. The input of the third inverter 44′ is coupled to the other terminal of the first transistor 42′. A terminal of the second transistor 46′ is coupled to the output of the third inverter 44′ and controlled by the wordline W. The input of the fourth inverter 48′ is coupled to the other terminal of the second transistor 46′ and the output of the third inverter 44′. The output of the fourth inverter 48′ is coupled to the first transistor 42′ and the input of the third inverter 44′. The third inverter 44′ includes a third transistor 440′ and a fourth transistor 442′; the fourth inverter 48′ includes a fifth transistor 480′ and a sixth transistor 482′. Because the inverter structure is a well known by a person having ordinary skill in the art, it is not described in more details here.
When the memory cell 40′ in FIG. 3 is not writing data, the signals in the wordline W are low-level signals, making the first and second transistors 42′, 44′ turned off (cutoff). At this moment, because the third inverter 44′ and the fourth inverter 48′ are cross-coupled, the data at the N1 node of the third inverter 44′ and the data at the N2 node of the fourth inverter 48′ are inversely latched to each other. When the memory cell 40′ writes, namely, when the memory cell 40′ writes “1”, the signal in the wordline W is high level (that is, “1”, and hence the first and second transistors 42′, 46′ are turned on, the signal in the dataline D is “1”, and the signal in the bitline DB is “0”. After the memory cell 40′ finishes writing data, the signal in the wordline W is changed to low level, turning off the first and second transistors 42′, 44′, and thereby latching the data.
With the progress of technological products, memory cells are demanded increasingly. In addition, the competition pressure on price and capacity increases as well. Thereby, memory cells with smaller unit area become more important, which means that a memory cell having fewer transistors is one of the objectives to work for.
Accordingly, the present invention provides a novel memory cell having a reduced circuit area, which uses fewer transistors to form a memory cell. Thereby, the problems described above can be solved.